The reverse engineering (RE) of an integrated circuit (IC) generally involves considering the physical structure of the circuit after fabrication and developing a schematic diagram thereof. Therefore, the reverse engineering of an integrated circuit may consist of a multi-step process wherein a schematic diagram of the IC is generated from the finished product. Until recently, RE of ICs has been implemented via manual techniques including the collection of images of circuit elements, the identification of circuit elements and the tracing of signals therebetween. As most schematics contain standard high-level components (like invertors, triggers, amplifiers, etc.), which in turn form more complicated but still standard and widely used modules, analysts must first deal with elementary components of the schematic to combine them into certain recognizable standard high-level components and modules. For example, during a typical RE process, basic circuit elements are extracted from topographical images, for example, and connections are made therebetween to re-generate the circuit's various components and modules. In order to complete this process, topographical imaging information from any and all layers of the IC is generally used. It will be apparent to one skilled in the art that the above discussion is a basic overview of the reverse engineering process and does not present all of the steps associated with or detail of the process of reverse engineering.
As stated above, the process of generating a schematic diagram from the extracted circuit elements has typically been a manual one where an analyst identifies the basic circuit elements and forms the connections therebetween to form the schematic diagram. Despite some efforts in developing automated systems for the generation of schematic diagrams, good quality schematics are still generated by such manual processes. In fact, it is sometimes considered that manually generated schematics are the standard to which schematics from other techniques of reverse engineering are to be compared.
Modern ICs however present many challenges for traditional reverse engineering techniques. These include, for example, but are not limited to, the ever-decreasing line dimensions of circuit features and the continually shrinking physical dimensions of circuit elements; the use of so-called auto-route techniques where circuit elements are located with regard to spatial considerations and not necessarily through logical placement with respect to their circuit operation; and other such considerations that will be apparent to the person skilled in the art. In their place, partially automated systems for image capture and the identification of circuit elements have been developed where these systems generally implement digital means for the storage and manipulation of information.
For instance, considerable resources have been invested into systems and methods for the extraction of circuit information from images of an IC. These systems and methods are adapted for the identification or extraction of circuit elements, the tracing of connectivity between extracted elements and the rendering of a schematic diagram of the IC. It is a goal of these systems to automate as many processes as possible, particularly in the area of design analysis. In each known system or method, however, there remain a number of manual steps that require operator intervention. Further, there are certain regions of circuitry that can make the analysis of a portion of the schematic difficult using such known systems and methods.
As stated above, reverse engineering of an integrated circuit can be roughly considered in terms of two basic processes; the extraction of circuit elements, including interconnects, and the generation of schematics therefrom. It is the later process that is of particular interest here. Some techniques have been developed for the automatic generation of schematic diagrams, or generally speaking, graph layout, wherein an energy function (e.g. a net congestion) is minimized. The resulting schematic, however, is typically of lower value for human comprehension than conventional high quality diagrams drawn by a human.
Therefore, there is a need for a new schematic generation system and method that overcomes some of the drawbacks of known techniques.
This background information is provided to reveal information believed by the applicant to be of possible relevance to the present invention. No admission is necessarily intended, nor should be construed, that any of the preceding information constitutes prior art against the present invention.